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With Design for Testability (aka "Design for
Test" or "DFT") it is all about creating a product that
it easier to develop and apply manufacturing tests to this is both for
production testing and diagnostic purposes.
Often I have seen DFT listed as a something that is just for IC design however it is much more than that. It is building a complete test strategy through out the design of the product and often interleaves with design for manufacture.
We live in a world where technology is shrinking and becoming more complex and in this world the fight for real estate is competitive, however we must not lose sight of the need to set room aside to enable the testing of the product in the most efficient way possible.
Design for Testability must take into account the finale state of the design ensuring that there are a number of test and debug features built in at design time that will aid the test process during the products life time.
This design forethrought can
include such things as a “debug-friendly” layout , with easily readable silk screen and via
holes to enable probing. Here is a good
1.This PCB has vias round U45 which would enable easy probing.
2.The silk screen is easy to read and where the parts
numbers can not be on the actual device they are layed out clearly nearby
Another consideration for Design for Testability is ensuring that the entire JTAG chain is connected. Often I have encountered PCBs with enabled parts that are unable to be accessed due to poor design.
I think the problem is that some people are only aware of the programming and processer emulation side of JTAG.
However these debug and programming tools that are commonly associated with JTAG are only a small aspect of what is possible. When considering Design for Testability designers should be aware of the ability to test beyond the boundary of the device.
This ability is known as the JTAG connection test.
The beauty of the JTAG connection test is that it can check that the connections around the JTAG enabled devices on a board are the same as those specified in the design.
This diagram for the JTAG connection test highlights the different tests that the device can carry out. The red lines show an incorrect connection and the reported failure by the device.
In the case of a reported short circuit -the pins of the device that are not meant to be connected are tested by driving one pin and checking that these values are not read on the other pins.
Missing pull resistors and ‘stuck-at’ faults can also be found by a connection test as well as faults involving logic devices whose behaviour can be described in a truth table.
While the main devices, such as processors and FPGAs, are normally JTAG enabled, there will be many devices in every design that are not.
Another important aspect of the JTAG connection test is that it will still provide excellent coverage for short circuit faults on the nets linking these non-JTAG devices to JTAG enabled devices; however it cannot check for open circuit faults at either the JTAG device or the non-JTAG device.
In order to add this open circuit coverage it is necessary to communicate with the peripheral device from boundary scan on the enabled device. If communication can be verified, there cannot be an open circuit fault. This type of testing can be very simple, for example lighting an LED and asking an operator to verify it has activated, or more complex, for example writing data into the memory array of a RAM and reading it back.